Product Summary

The Z84C4406VEC is a serial input/output controller. Full interfacing is aprovide for CPU or DMA control. In addition to data communication, the circuit can handle virtually all types of serial I/O with fast, or slow peripheral devices. While designed primarily as a member of the Z84C4406VEC, its versatility makes it well suited to many other CPUs. The Z84C4406VEC uses a single +5V power supply and the standard the device single-phase clock. The SIO/0, SIO/1 and SIO/2 are packaged in a 40-pin DIP, the SIO/4 is packaged in a 44-pin PCC and the SIO/3 is packaged in a 44-pin QFP. Note the SIO/3 is only available in CMOS and in QFP package.

Parametrics

Z84C4406VEC absolute maximum ratings: (1)Voltage in VCC with respect to VSS: -0.3V to +0.7V; (2)Voltage on all inputs with rewspect to VSS: -0.3V to VCC +0.3V; (3)Storage temperature: -65℃ to +150℃.

Features

Z84C4406VEC features: (1)Two independent, with separate control and status lines ; (2)Data rate in the ×1 clock mode of 0 to 2.0M bits/second with a 10MHz clock; (3)NMOS version for cost sensitive performance solutions, CMOS version requiring low power consumption; (4)NMOS Z0844×04-4MHz to 6.17MHz (where ×is the designator for the option: 0,1,2, or 4); (5)CMOS Z84C4×06, DC to 6MHz, Z84C4×08, DC to 8MHz, Z84C4×1, DC to 10MHz; (6)Sybchronous products everything necessary for complete messages to 5, 6, 7, or 8 bits/character; (7)Sybchronous products everything necessary for complete messages to 5, 6, 7, or 8 bits/character, including IBM bisybc, SDLC, HDLC, CCITT-X25 and others automatic CRC generation/checking, sync chaeacter and zero insertion/deletion, about generation and flag insertion; (8)Receiver data registers quadruply buffered transmitter regustera doubly buffered.

Diagrams

Z84C4406VEC block diagram

Image Part No Mfg Description Data Sheet Download Pricing
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Z84C4406VEC
Z84C4406VEC

ZiLOG

Microprocessors (MPU) 6MHz CMOS SIO/4 XT

Data Sheet

Negotiable 
Z84C4406VEC00TR
Z84C4406VEC00TR


IC Z80 MPU SIO 44PLCC

Data Sheet

Negotiable