TL16C550CN

Product Summary

The TL16C550CN is a asynchronous communications element (ACE) with autoflow control, which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the device on power up, the TL16C550CN can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The TL16C550CN stores up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS input signals.

Parametrics

TL16C550CN absolute maximum ratings: (1)Supply voltage range, VCC: -0.5 V to 7 V; (2)Input voltage range at any input, VI: -0.5 V to 7 V; (3)Output voltage range, VO: -0.5 V to 7 V; (4)Operating free-air temperature range, TA: 0℃ to 70℃; (5)Storage temperature range, Tstg: -65℃ to 150℃; (6)Case temperature for 10 seconds, TC: FN package: 260℃; (7)Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N or PT package: 260℃.

Features

TL16C550CN features: (1)Programmable Auto-RTS and Auto-CTS; (2)In Auto-CTS Mode, CTS Controls Transmitter; (3)In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS; (4)Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop; (5)Capable of Running With All Existing TL16C450 Software; (6)After Reset, All Registers Are Identical to the TL16C450 Register Set; (7)Up to 16-MHz Clock Rate for up to 1-Mbaud Operation; (8)In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data; (9)Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 –1) and Generates an Internal 16× Clock; (10)Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream; (11)5-V and 3.3-V Operation; (12)Independent Receiver Clock Input; (13)Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled; (14)Fully Programmable Serial Interface Characteristics: 5-, 6-, 7-, or 8-Bit Characters; Even-, Odd-, or No-Parity Bit Generation; (15)and Detection; 1-, 1 1/2-, or 2-Stop Bit Generation; Baud Generation (dc to 1 Mbit/s); (16)False-Start Bit Detection; (17)Complete Status Reporting Capabilities; (18)3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus; (19)Line Break Generation and Detection; (20)Internal Diagnostic Capabilities: Loopback Controls for Communications Link Fault Isolation; Break, Parity, Overrun, and Framing Error Simulation; (21)Fully Prioritized Interrupt System Controls; (22)Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD).

Diagrams