(Hong Kong)
Product Summary
The MC10EP33DR2 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single–ended or AC coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01mF capacitor. The reset pin is asynchronous and is asserted on the rising edge. Upon power–up, the internal flip–flops will attain a random state; the reset allows for the synchronization of multiple the MC10EP33DR2’s in a system.
Parametrics
MC10EP33DR2 absolute maximum ratings: (1)VEE Power Supply (VCC = 0V): –6.0 to 0 VDC; (2)VCC Power Supply (VEE = 0V): 6.0 to 0 VDC; (3)VI Input Voltage (VCC = 0V, VI not more negative than VEE): –6.0 to 0 VDC; (4)VI Input Voltage (VEE = 0V, VI not more positive than VCC): 6.0 to 0 VDC; (5)Iout Output Current: Continuous 50mA, Surge 100mA; (6)IBB VBB Sink/Source Current: ± 0.5 mA; (7)TA Operating Temperature Range: –40 to +85 ℃; (8)Tstg Storage Temperature: –65 to +150 ℃; (9)θJA Thermal Resistance (Junction–to–Ambient): Still Air 190℃/W, 500lfpm 130℃/W; (10)θJC Thermal Resistance (Junction–to–Case): 41 to 44 ± 5% ℃/W; (11)Tsol Solder Temperature (<2 to 3 Seconds: 245℃ desired): 265 ℃.
Features
MC10EP33DR2 features: (1)320ps Propagation Delay; (2)3 GHz Typical Toggle Frequency; (3)PECL mode: 3.0V to 5.5V VCC with VEE = 0V; (4)ECL mode: 0V VCC with VEE = -3.0V to -5.5V; (5)Internal Input Resistors: Pulldown on D, D; (6)Q Output will default LOW with inputs open or at VEE; (7)ESD Protection: >4KV HBM, >200V MM; (8)VBB Output; (9)New Differential Input Common Mode Range; (10)Moisture Sensitivity Level 1, Indefinite Time Out of Drypack; (11)Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34; (12)Transistor Count = 91 devices.
Diagrams
| Image | Part No | Mfg | Description |  |
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 MC10EP33DR2 |
ON Semiconductor |
Multipliers / Dividers 3.3V/5V ECL Divide |
Data Sheet |
Negotiable |
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MC10EP33DR2G |
ON Semiconductor |
Clock Drivers & Distribution 3.3V/5V ECL Divide By 4 Divider |
Data Sheet |
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