(Hong Kong)
Product Summary
The MC100EL35DR2 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. The MC100EL35DR2 contains temperature compensation.
Parametrics
MC100EL35DR2 absolute maximum ratings: (1)VCC PECL Mode Power Supply VEE = 0 V: 8 V; (2)VEE NECL Mode Power Supply VCC = 0 V: -8 V; (3)VI PECL Mode Input Voltage: 6V; (4)NECL Mode Input Voltage: -6V; (5)Iout Output Current Continuous: 100mA; (6)TA Operating Temperature Range: -40 to +85 °C; (7)Tstg Storage Temperature Range: -65 to +150 °C.
Features
MC100EL35DR2 features: (1)525 ps Propagation Delay; (2)2.2G Hz Toggle Frequency; (3)ESD Protection: > 1 kV Human Body Model, > 100 V Machine Model; (4)PECL Mode Operating Range: VCC = 4.2 V to 5.7 with VEE = 0 V; (5)NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V; (6)Internal Input Pulldown Resistors on J, K, CLK, and R; (7)Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test; (8)Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D; (9)Flammability Rating: UL-94 V-0 @ 0.125 in, Oxygen Index 28 to 34; (10)Transistor Count = 81 devices; (11)Pb-Free Packages are Available.
Diagrams
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Pricing (USD) |
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 MC100EL35DR2 |
ON Semiconductor |
Flip Flops 5V ECL JK Type |
Data Sheet |
Negotiable |
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MC100EL35DR2G |
ON Semiconductor |
Flip Flops 5V ECL JK Type |
Data Sheet |
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