(Hong Kong)
Product Summary
The CY7C1329-100AC is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. All synchronous inputs of CY7C1329-100AC pass through input registers controlled by the rising edge of the clock. All data outputs of CY7C1329-100AC pass through output registers controlled by the rising edge of the clock.
Parametrics
CY7C1329-100AC maximum ratings: (1) Storage Temperature: -65Power Applied to +150°C; (2) Ambient Temperature with Power Applied: -55 °C Power Applied to +125 °C; (3) Supply Voltage on VDD Relative to GND : -0.5V to +4.6V; (4) DC Voltage Applied to Outputs in High Z State: -0.5V to VDDQ +0.5V; (5) DC Input Voltage: -0.5V to VDQQ:+ 0.5V; (6) Current into Outputs (LOW) : 200mA; (7) Static Discharge Voltage (per MIL-STD-883, Method 3015) : ＞2001V; (8) Latch-Up Current: ＞200mA.
Features
CY7C1329-100AC features: (1) Supports 133-MHz bus for Pentium (TM) and PowerPC® operations with zero wait states; (2) Fully egistered inputs and outputs for pipelined; (3) 64K x 32 common I/O architecture; (4) Single 3.3V power supply; (5) Fast clock-to-output times: 4.2ns (for 133-MHz device) ; 5.5 ns (for 100-MHz device) ; 7.0ns (for 75-MHz device) ; (6) User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences; (7) Separate processor and controller address strobes; (8) Synchronous self-timed writes; (9) Asynchronous output enable; (10) JEDEC-standard 100 TQFP pinout; (11) ZZ Sleep Mode option and Stop Clock option.
Diagrams
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 CY7C1329-100AC |
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Negotiable |
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